投稿時間:2021-04-09 10:34:25 RSSフィード2021-04-09 10:00 分まとめ(40件)

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IT	気になる、記になる…	Satechi、｢マグネットワイヤレス充電ケーブル｣などの対象製品を最大20％オフで販売する3日間限定セールを開催中	https://taisy0.com/2021/04/09/138741.html	apple	2021-04-09 00:49:40
IT	気になる、記になる…	Apple、ドイツのベルリンに2店舗目の直営店をオープンか	https://taisy0.com/2021/04/09/138725.html	apple	2021-04-09 00:37:00
IT	ITmedia 総合記事一覧	[ITmedia ビジネスオンライン] 羽田空港に「PCR検査センター」、15分で結果が分かる	https://www.itmedia.co.jp/business/articles/2104/09/news053.html	itmedia	2021-04-09 09:40:00
IT	ITmedia 総合記事一覧	[ITmedia News] 米商務省、中国スパコン組織7件をエンティティリストに	https://www.itmedia.co.jp/news/articles/2104/09/news052.html	itmedia	2021-04-09 09:36:00
IT	ITmedia 総合記事一覧	[ITmedia News] 机や太ももの上でキーボードなしタイピング　指輪型「TelemetRing」、東大とMicrosoftが開発	https://www.itmedia.co.jp/news/articles/2104/09/news051.html	文字入力	2021-04-09 09:34:00
TECH	TechAcademyマガジン	プログラミングが学べる「龍谷大学」について	https://techacademy.jp/magazine/61737	プログラミングが学べる「龍谷大学」について本記事ではプログラミングが学べる「龍谷大学」について紹介します。	2021-04-09 00:15:30
AWS	AWS Machine Learning Blog	Win a digital car and personalize your racer profile on the AWS DeepRacer console	https://aws.amazon.com/blogs/machine-learning/win-a-digital-car-and-personalize-your-racer-profile-on-the-aws-deepracer-console/	Win a digital car and personalize your racer profile on the AWS DeepRacer consoleAWS DeepRacer is the fastest way to get rolling with machine learning giving developers the chance to learn ML hands on with a th scale autonomous car D virtual racing simulator and the world s largest global autonomous car racing league With the AWS DeepRacer League Virtual Circuit now underway developers have five times more opportunities …	2021-04-09 00:03:14
AWS	AWS Japan Blog	AWS Control Tower が東京リージョンでご利用いただけるようになりました	https://aws.amazon.com/jp/blogs/news/aws-control-tower-tokyo/	LandingZone従来東京リージョンでは、ControlTowerが利用できなかったため、LandingZoneという、セキュアなマルチアカウントのAWS環境をより迅速に設定できるようにするソリューションが提供されていました。	2021-04-09 00:54:28
AWS	AWS Japan Blog	AWS における Amazon SageMaker と AWS Data Exchange を使ったアルゴリズム取引	https://aws.amazon.com/jp/blogs/news/algorithmic-trading-on-aws-with-amazon-sagemaker-and-aws-data-exchange/	具体的には、キャピタルマーケット業界における企業がAWSに移行し、オンプレミスソリューションをクラウドに拡張したり、クラウドネイティブソリューションを構築したりすることに関し、さまざまなユースケースやメリットがあります。	2021-04-09 00:26:34
AWS	AWS Japan Blog	ニュース記事 : Morningstar、機械学習の適用を加速するためのグローバル AWS DeepRacer 企業コンペティションを開始	https://aws.amazon.com/jp/blogs/news/in-the-news-morningstar-launches-global-aws-deepracer-corporate-competition-to-accelerate-application-of-machine-learning/	Morningstarの技術部門のを含むか国の名を超える従業員が、AWSDeepRacerリーグで約チームを結成しており、機械学習機能を持つスケールのレーシングカーのプログラミングとそのレーシングを行っています。	2021-04-09 00:25:54
AWS	AWS Japan Blog	AWS Step Functions コールバックを利用した外部システム連携	https://aws.amazon.com/jp/blogs/news/integrating-aws-step-functions-callbacks-and-external-systems/	StepFunctionsを使用すると、AWSLambdaやAmazonECSのようなサービスを機能豊富なアプリケーションに統合するワークフローを設計および実行できます。	2021-04-09 00:06:25
デザイン	コリス	イラストのディレクション本がついに発売！イラストの仕事に携わる人は目を通しておいて損のない一冊 -たのしく、イラストディレクション！	https://coliss.com/articles/book-review/isbn-9784802511254.html	続きを読む	2021-04-09 00:36:41
python	Pythonタグが付けられた新着投稿 - Qiita	Django Filterの使い方	https://qiita.com/shibafu/items/9ceb737c8d29307743ef	DjangoFilterの使い方モデルからエンティティを取得する方法には、getとFilterの二つ方法があるDjangoのモデル機能、便利なんですが、値を取り出すとき、getだとエラーになる場合が多いので、メモですgetはエンティティが取得できない場合、例外になるservicepyHogeModelobjectsgetnameなまえこの場合、ヒット数がだと例外で落ちちゃいますDoesNotExitエラーで、filterを使いましょうという話servicepyクエリセットで受け取るresultQuerySetHogeModelobjectsfilternameなまえ値を取り出す。	2021-04-09 09:57:09
python	Pythonタグが付けられた新着投稿 - Qiita	globで指定したディレクトリ以下から特定の拡張子ファイルのみ取得	https://qiita.com/cv_carnavi/items/48c1aaa1a95324b90d71	globで指定したディレクトリ以下から特定の拡張子ファイルのみ取得Pythonからglobでを使った再帰的な処理がサポートされました。	2021-04-09 09:39:44
python	Pythonタグが付けられた新着投稿 - Qiita	Anacondaの商用利用有償化に際して: pipでIntel Math Kernel Library (MKL)をサクッと入れる (Windows)	https://qiita.com/Koshka/items/9226ef69676d18216fa1		2021-04-09 09:08:54
Program	[全てのタグ]の新着質問一覧｜teratail（テラテイル）	if文でRemoveが機能しない	https://teratail.com/questions/332336?rss=all	条件としては追加ボタンを押しているときに自動削除ボタンを押し実行すると削除されるという仕組みにしたいです。	2021-04-09 09:58:43
Program	[全てのタグ]の新着質問一覧｜teratail（テラテイル）	Nuxt.jsでmethodsを利用したい	https://teratail.com/questions/332335?rss=all	Nuxtjsでmethodsを利用したい現在、Nuxtjsの学習をしておりmethodsを利用しボタンをクリックした際にメッセージが反転するように実装したいです。	2021-04-09 09:46:12
Program	[全てのタグ]の新着質問一覧｜teratail（テラテイル）	noindexのページではdescriptionは不要？	https://teratail.com/questions/332334?rss=all	noindexのページではdescriptionは不要初めてWebページを公開する初心者です。	2021-04-09 09:43:25
Program	[全てのタグ]の新着質問一覧｜teratail（テラテイル）	Windowsアプリ 冗長化（二重化）手法につきまして	https://teratail.com/questions/332333?rss=all	Windowsアプリ冗長化二重化手法につきまして同じLAN上の台のPCに同じアプリを導入して起動しておき、一方がサービス中の際には他方は待機し、一方のサービスが停止されたりアプリが終了されると他方がサービスを開始する、というような二重化を実現しようと思います。	2021-04-09 09:34:55
Program	[全てのタグ]の新着質問一覧｜teratail（テラテイル）	npm run start　エラー：react-scriptsのバージョンの違い	https://teratail.com/questions/332332?rss=all	npmrunstartエラーreactscriptsのバージョンの違い前提・実現したいことreactを使いシステムを開発しています。	2021-04-09 09:26:40
Program	[全てのタグ]の新着質問一覧｜teratail（テラテイル）	エイリアステンプレートをかませた場合の型推論	https://teratail.com/questions/332331?rss=all		2021-04-09 09:25:18
Program	[全てのタグ]の新着質問一覧｜teratail（テラテイル）	AWS S3を使ってサイトに独自ドメインを割り当てるがうまくいかない	https://teratail.com/questions/332330?rss=all	AWSSを使ってサイトに独自ドメインを割り当てるがうまくいかないこの度、ホームページをAWSのSと、routeを使い独自ドメインを持ったホームページを作成しようと考えています。	2021-04-09 09:15:08
Program	[全てのタグ]の新着質問一覧｜teratail（テラテイル）	typescriptのtypeのキー一覧を取得したい	https://teratail.com/questions/332329?rss=all	typescriptのtypeのキー一覧を取得したいいつもお世話になっております。	2021-04-09 09:05:55
AWS	AWSタグが付けられた新着投稿 - Qiita	はじめてのEC2インスタンス	https://qiita.com/miyuki_samitani/items/61e1548cb61f4053e78d	ECインスタンスはイメージではインスタンスサーバとストレージHDDが別の考えなのでデフォルトではインスタンスを削除したときHDDは自動的に削除されません。	2021-04-09 09:10:03
Git	Gitタグが付けられた新着投稿 - Qiita	Git ローカルリポジトリの最新のコミットを取り消す	https://qiita.com/miriwo/items/1a903fe122546b20c349	Gitローカルリポジトリの最新のコミットを取り消す目的ローカルリポジトリの最新のコミットを取り消す方法を個人メモ的にまとめる情報コミットをリバートするのではなく完全に取り消す方法を記載する。	2021-04-09 09:57:18
海外TECH	DEV Community	Understanding Atomics and Memory Ordering	https://dev.to/kprotty/understanding-atomics-and-memory-ordering-2mom	Understanding Atomics and Memory OrderingAtomics and Memory Ordering always feel like an unapproachable topic In the sea of poor explanations I wish to add another by describing how I reason about all of this mess This is only my understanding so if you need a better formal explanation I recommend reading through the memory model for your given programming language In this case it would be the C Memory Model described at cppreference com Shared MemorySoftware and hardware is getting closer to the limits of performance when it comes to single threaded execution of code In order to continue scaling compute performance a popular solution is to introduce multiple single threaded execution units or multi threading This form of computation manifests itself at different abstraction levels from multiple cores in a CPU to multiple CPUs in a machine and even multiple machines across a network This post will be focusing more on cores in a CPU referring to them as “threads For some workloads the tasks can be divided cleanly and split off to the threads for execution Such tasks are known as embarrassingly parallel and need not communicate with each other This is the ideal that multithreaded algorithms should strive for since it takes advantage of all the existing optimizations available for single threaded execution However this isn t always possible and it s sometimes necessary for tasks to communicate and coordinate with each other which is why we need to share memory between threads Communication is hard when your code is running in a preemptive scheduling setting Such an environment means that at any point your code can be interrupted in order for other code to run In applications the operating system kernel can decide to switch from running your program to run another In the kernel hardware can switch from running kernel code to running interrupt handler code Switching tasks around like this is known as concurrency and in order to synchronize communicate we need a way to exclude that concurrency for a small time frame or we risk operating with incomplete partial data AtomicsFortunately CPUs supply software with special instructions to operate on shared memory which can t be interrupted These are known as atomic memory operations and fit into three categories Loads Stores and ReadModifyWrites RMW The first two are self explanatory RMW is also pretty descriptive it allows you to load data from memory operate on the data and store the result back into memory all atomically You may know RMW operations as atomic increment swap or compare and swap To do something atomically means that it must happen or be observed to happen in its entirety or not at all This implies that it cannot be interrupted When something is atomic tearing i e partial completion of the operation cannot be observed Atomic operations allow us to write code that can work with shared memory in a way that s safe against concurrent interruption Another thing about atomics is that they re the only sound i e correctly defined way to interact with shared memory when there s at least one writer and possibly multiple readers writers to the shared memory Trying to do so without atomics is considered a data race which is undefined behavior UB UB is the act of relying on an assumption outside of your target program model in our case the C memory model Doing so is unreliable as the compiler or cpu is allowed to do anything outside of its model Data races and the UB it implies isn t just a theoretical issue One of the single threaded optimizations I mentioned earlier involves either the CPU or the compiler caching memory reads and writes If you don t use atomic operations the operation itself could be ellided and replaced with its cached result which could break the logic of your code fairly easily should be an atomic load but its data racewhile not load bool continue a potential single threaded optimizationcached load bool while not cached possibly infinite loop continue ReorderingAtomics solve communication only on atomically accessed memory but not all memory being communicated can be accessed atomically CPUs generally expose atomic operations for memory that s at most a few bytes large Trying to do any other sort of general purpose memory communication means we need a way to make this memory available to threads with other means Making memory available to other threads is actually trickier than it sounds Let s check out this code example data Nonehas data False Thread write amp data hello atomic store amp has data True Thread if atomic load amp has data d read amp data assert d hello At first glance this looks like it would work Even if each thread were preempted between each instruction line of code here it seems the assert should always succeed Based on my wording you ve probably caught on that this assert can actually fail The reason for this is due to another single threaded optimization called reordering Hardware CPU or software the compiler as well can decide to move around i e “reorder your code and instructions any way they please as long as the end result is the same as the source code s intent This sort of “instruction scheduling freedom allows for a variety of optimizations to take place One example of reordering is via speculative execution This is when the CPU starts executing code that hasn t been reached yet in the opportunistic chance that the results can be ready when that code is eventually reached This is an amazing single threaded throughput optimization but it means that the atomic store can be started before the write or the read can be started before the atomic load both of which could make the assert fail Another example of reordering is by CPU caches CPUs don t read write directly to shared memory since that s relatively slow Instead each CPU core has its own fast access local memory called cache Most memory operations are performed on a CPU s cache and eventually flushed to refreshed from to other caches in a process called Cache Coherency In our example the atomic store could have flushed from cache to shared memory before the write does e g if flushing is done LIFO or the atomic load could refresh in cache before the read is both of which could make the assert to fail Even the compiler can reorder instructions but only those without relationships called dependencies One instruction line of code is said to depend on a previous instruction if it uses the result from the previous one or if the previous one is a side effect The compiler is free to reorder instructions anywhere before their dependency but not after This means a b can be reordered to b a which keeps the same semantics achieving the same thing since a and b don t share a dependency with each other If it were instead a b a then a can t be moved after b since it wouldn t make logical sense as b has a dependency on a In our example atomic store doesn t have a dependency on write so it can be moved around which can make the assert to fail At this point it should be clear that instruction reordering is a thing and when interacting with shared memory you have to be aware of it The problem is that atomic operations on their own don t prevent reordering We need an additional concept for atomics to do this In C atomic operations take in another parameter called memory ordering which helps solve this problem In our previous code example there were two main issues one of reordering and one of visibility Memory orderings solve them by preventing code from being reordered around atomic operations and ensures that certain data or operations become visible or get conceptually flushed reloaded from cache Lets see what this looks like Release and AcquireWe ll introduce two types of memory orderings for now Acquire and Release Release goes on atomic stores and ensures that all memory operations declared before it actually happen before it Acquire goes on atomic loads and ensures all memory operations declared after actually happen after it This solves the reordering problem We then declare one more constraint All memory operations before a given Release can be observed to happen before a matching Acquire You could think of it as changes from the Release becoming visible in a git push manner to the Acquire which does a sort of git pull This solves the visibility problem Let s add these to our code example data Nonehas data False Thread write amp data hello atomic store amp has data True Release Thread if atomic load amp has data Acquire d read amp data assert d hello Note that Release and Acquire don t do any sort of waiting or blocking for the data to become ready They aren t replacements for known synchronization primitives Instead they ensure that if our atomic load sees has data to be True then it s also guaranteed to see write amp data hello thanks to the matching Acquire and Release barriers so our assert should never fail For ReadModifyWrite RMW atomic instructions they can also take in a memory ordering called AcqRel Given RMW operations conceptually do both an atomic load and an atomic store AcqRel makes both operations Acquire and Release respectively This is useful when you want an atomic operation which both makes memory available to other threads via Release and sees memory made available by other threads via Acquire Fences and VariablesYou ll notice that i ve been saying matching Acquire Release For our examples the matching is from the load and store using the same atomic variable amp has data Release and Acquires on different atomic variables don t synchronize with each other it has to be the same atomic variable There s an exception to the rule which manifests itself as fences Fences are a way to establish memory orderings of normal and atomic memory operations without necessarily associating with one given memory op Fences are a bit tricky for me as I have a hard time describing them but they essentially create the happens before relationship to surround atomics in a way that corresponds to the memory ordering being used A fence Release creates a happens before relationship with another fence Acquire A fence Release makes subsequent non Release atomic stores into Release if they have a matching Acquire atomic load or matching fence Acquire A fence Acquire makes previous non Acquire atomic loads into Acquire if they have a matching Release atomic store or matching fence Release Here s an example of how we could substitute the per operation memory orderings with fences data Nonehas data False Thread write amp data hello fence Release atomic store amp has data True Thread if atomic load amp has data fence Acquire d read amp data assert d hello Case Study MutexYou may have also noticed that this section is called Release and Acquire instead of Acquire and Release This is done intentionally as having Acquire first often construdes the happens before relationship Instead of thinking about lock Acquire and unlock Release it should instead be thought about unlock Release making critical section changes available to lock Acquire mutex Mutex data None Thread assume locked data hello fence Release mutex unlock Thread assume unlocked mutex lock fence Acquire assert data hello The Release ordering for a mutex only serves to Release the changes to the next mutex locker who Acquires the previously released changes by the last mutex unlocker The canonically backwards relationship better demonstrates the happens before relationship between Release and Acquire compared to just saying lock acquires and unlock releases What we have created here is called a Partial Ordering It s an ordering between two sets of memory operations The reason it s partial is because it orders between sets instead of the individual operations themselves The operations before a Release don t need to be observed happening in the order they were described for an Acquire they just need to be observed to have happened at all Sequential ConsistencyThere are cases when you need certain atomic operations to be observed in a given order between each other What we need now is a Total Ordering This ensures there s some defined ordering between the operations themselves rather than a set of operations and is what the SeqCst memory ordering is used for Let s see another code example head tail buf Thread steal h atomic load amp head t atomic load amp tail if t gt h item buf h if atomic cas amp head h h return item return None Thread pop t tail atomic store amp tail t h atomic load amp head if t gt h return buf t if t h and atomic cas amp head h t return buf t atomic store amp tail t return NoneThis is code taken from the implementation of a LIFO Deque by Chase Lev What it does isn t necessarily important but it serves as a nice example when SeqCst is actually needed For pop we want to ensure that the store to tail is observed to happen before the load to head If not pop may not see the items removed from steal Lets try to apply Acquire and Release to pop atomic store amp tail t Release h atomic load amp head Acquire This doesn t exactly do what we want Release prevents stuff before the store being reordered after and Acquire prevents stuff after the load being reordered before it There s no guarantee that the store and load themselves can t be reordered before after each other other memory operations X store release load acquire X v other memory operationsIn order to ensure that the atomic store and load stay in their declared order we either need an Acquire barrier on the store which we can semantically achieve using an RMW operation with AcqRel atomic swap amp tail t AcqRel or we need SeqCst atomic store amp tail t SeqCst h atomic load amp head SeqCst SeqCst does two things here It acts as a Release for stores Acquire for loads as before but it also ensures a total ordering between all SeqCst operations The total ordering ensures that the store will be seen before the load for other totally ordered operations Because total ordering only applies to other SeqCst ops we need to apply SeqCst to everything that relies on the total ordering This includes the atomic load cas in pop as well as the atomic loads cas in steal The total ordering property also extends to fence SeqCst so we can use those to achieve the same reordering effects steal t atomic load amp tail fence SeqCst h atomic load amp head pop atomic store amp tail t fence SeqCst h atomic load amp head To be clear SeqCst shouldn t be used to somehow gain Acquire on stores or Release on loads That can lead to incorrect usage store SeqCst load Acquire doesn t ensure that the store will not be reordered after the load since the load isn t a part of its total ordering it s not SeqCst as well It should be used instead to enforce a total ordering between multiple atomic variables and introduce partial ordering Acquire Release as before which together can achieve the same effect More emphasis that total ordering only applies to other SeqCst atomic operations or to surrounding ops in relation to fence SeqCst See this issue for more warnings Weak orderingsIn most cases you probably don t need total ordering on operations for multiple atomic variables Having the requirement for SeqCst is pretty rare In practice SeqCst is unfortunately often overused and a problematic sign that the programmer wasn t sure what memory ordering to use Anyway when you don t want total ordering over different atomic variables and don t need partial ordering you should reach for the Relaxed memory ordering also known as Monotonic under LLVM All this does is ensure a total order between all atomic operations to the same atomic variable In other words other memory operations not on the same memory location can be reordered around it So store X load Y can be reordered around each other but store Y load Y can t All other memory orderings Acquire Release AcqRel SeqCst inherit the Relaxed property of single variable total ordering and are known to be stronger than it Relaxed is useful for things like counters or generic single atomic data that you just read update and check out You cannot use this to synchronize other normal or atomic memory operations There are even cases where you don t need the total ordering on the same atomic variable itself and just want to perform some memory operation atomically i e to be free of data races For this you would use the LLVM s Unordered memory ordering The need for this ordering is even more rare than the need for SeqCst Unordered also isn t even present in the C memory model it only gets as weak as Relaxed Hardware QuirksOn modern CPU instruction set architectures ISA normal memory operations are atomic by default The upside is that you don t pay a price for Relaxed Unordered memory orderings or atomic loads stores vs normal operations The downside is that data races don t exist for the ISA so it s harder to know if you have one or not Fortunately there are tools which can instrument your memory accesses to detect data races like LLVM s ThreadSanitizer TSAN Certain CPU ISAs are known to have Total Store Ordering TSO This includes things like x and SPARC Here upon normal memory operations being atomic they also get partial ordering for free This means loads are Acquire by default and stores are Release by default As before you get the benefit of Release Acquire operations having no overhead besides inhibiting compiler optimizations but it also has its downsides In this case it lets you be pretty free with orderings so your Relaxed code that should be Release Acquire will work there but break on other architectures making it easy to write code with incorrect memory orderings The other architectures mentioned are called Weakly Ordered ISAs This includes things like ARM AARCH POWERPC RISCV MIPS etc Here loads and stores are still atomic by default but they re only Relaxed and you pay prices for Acquire Release This means that getting ordering wrong gives you a higher chance of observing incorrect behavior The weaker default orderings theoretically allow for more reordering opportunities by the CPU but this doesn t appear to matter in practice given how much better modern x CPUs are for cross core communication in the general case When it comes to Sequential Consistency however there aren t really any platforms where you get this for free fence SeqCst in particular is generally the most costly since it often requires a full barrier to implement which prevents all forms of reordering On x it s achieved with mfence although it can be done cheaper using lock prefixed instructions if you re not synchronizing write combined memory instructions SeqCst loads stores often require either promotion to RMW ops or Acquire Release barriers to keep their semantics This may be why SeqCst operations are rumored to be slow they really aren t ConclusionWorking with atomic operations requires reasoning about memory very differently than you would normally You have to take into account both concurrency for the validity of your atomic algorithm and reordering visibility for the validity of your algorithm s memory access It s no wonder that it s considered a challenging topic to tackle Hopefully you have Acquired some of this Released information in a way which gives you more visibility into how all of this stuff works There s more to discuss with atomics than presented here such as how to build correct atomic data structures handling concurrent memory reclamation and reducing synchronization These are all interesting in their own right but should be saved for another time	2021-04-09 00:33:25
海外TECH	DEV Community	Introducing the GitHub Security Overview | GitHub Security Center	https://dev.to/n3wt0n/introducing-the-github-security-overview-github-security-center-56dm	Introducing the GitHub Security Overview GitHub Security CenterThe new GitHub Security Overview commonly referred to as GitHub Security Center consolidates in one place all the GitHub Advanced Security recommendations like the GitHub Code scanning results the GitHub Secret Scanning etc VideoTo showcase this important and long awaited new feature I ve create a video in which I go through how to access and how to use all the new features Watch the full video here Link to the video Let me know below what you think Do you have any other questions about Linters and Linting Stay tuned because I will soon have another post and video about the GitHub Super Linter Like share and follow me for more content YouTube Buy me a coffeePatreonMerchFacebook page‍GitHubTwitterLinkedInPodcast	2021-04-09 00:03:35
海外TECH	Engadget	Neuralink's brain-computer interface demo shows a monkey playing Pong	https://www.engadget.com/monkey-mindpong-link-003709524.html	Neuralink x s brain computer interface demo shows a monkey playing PongElon Musk s Neuralink is building brain computer interfaces like the one that allows this monkey to control a game of Pong with its thoughts	2021-04-09 00:37:09
金融	日本銀行：RSS	庶務職員（自動車運転員）の募集について	http://www.boj.or.jp/announcements/release_2021/rel210409b.htm	運転	2021-04-09 10:00:00
海外ニュース	Japan Times latest articles	Tokyo, Kyoto and Okinawa to get tougher steps to fight coronavirus	https://www.japantimes.co.jp/news/2021/04/09/national/science-health/covid-19-in-japan-tokyo-yoshihide-suga/	capital	2021-04-09 09:11:16
ニュース	BBC News - Home	Coronavirus: Cost of testing 'is too much for people to travel'	https://www.bbc.co.uk/news/business-56682226	coronavirus	2021-04-09 00:01:52
ニュース	BBC News - Home	George Floyd died from lack of oxygen, not fentanyl, says expert	https://www.bbc.co.uk/news/world-us-canada-56670912	argument	2021-04-09 00:19:34
ニュース	BBC News - Home	Overseas health workers to get free UK visa extension, says Home Office	https://www.bbc.co.uk/news/uk-politics-56680286	workers	2021-04-09 00:11:50
ニュース	BBC News - Home	'Satan Shoes' to be recalled as Nike agrees to settle lawsuit	https://www.bbc.co.uk/news/business-56684773	refunds	2021-04-09 00:26:46
ニュース	BBC News - Home	Amazon holds early lead in historic union election	https://www.bbc.co.uk/news/business-56657595	alabama	2021-04-09 00:04:31
ニュース	BBC News - Home	Covid-19: Bilston traders 'optimistic' for reopening of shops	https://www.bbc.co.uk/news/uk-england-birmingham-56589661	essential	2021-04-09 00:37:12
LifeHuck	ライフハッカー［日本版］	「画面の見すぎ」による目への影響と正しい目のケア方法	https://www.lifehacker.jp/2021/04/232628what-happens-to-your-eyes-when-you-stare-at-screens-all.html	画面	2021-04-09 10:00:00
北海道	北海道新聞	＜直道スタイル　道政１期目折り返し＞上　発信重視奏功、支持「８５％」	https://www.hokkaido-np.co.jp/article/531236/	鈴木直道	2021-04-09 09:17:33
マーケティング	AdverTimes	タップするその言葉はUXライティング	https://www.advertimes.com/20210409/article346358/	言葉	2021-04-09 01:00:21
マーケティング	AdverTimes	「明治プロビオヨーグルトLG21」新CMで片桐仁が長男・次男と共演	https://www.advertimes.com/20210409/article346285/	明治プロビオヨーグルト	2021-04-09 00:30:57